Coherency tracking apparatus and method for an attached coprocessor or accelerator

ABSTRACT

An apparatus and method for hybrid software-hardware coherency. An apparatus comprises one or more processing elements to process data; a memory controller to couple the one or more processing elements to a device memory; an interconnect to couple the one or more processing elements to a host processor memory and to couple a host processor to the device memory; one or more device caches to store cache lines read from the host processor memory and/or the device memory; coherency circuitry to manage an ownership indication for each cache line, the ownership indication to be set to a first value to indicate ownership by the host processor and to be set to a second value to indicate ownership by the processing device, wherein the coherency circuitry is to transfer ownership of a first cache line from the processing device to the host processor by updating the ownership indication from the second value to the first value, the coherency circuitry to provide indirect access to the cache line by the processing device while the ownership indication is set to the first value, the coherency circuitry to maintain the ownership indication at the first value until receiving a request to change the ownership indication.

BACKGROUND Field of the Invention

The embodiments of the invention relate generally to the field ofcomputer processors. More particularly, the embodiments relate to acoherency tracking apparatus and method for an attached coprocessor oraccelerator.

Description of the Related Art

The Compute Express Link (CXL) is a coherent link for attachingaccelerators. This link supports three types of protocols: (i) CXL.iowhich is semantically equivalent to a PCI Express (PCIe) link; (ii)CXL.cache which lets the accelerator generate coherent requests to hostmemory; and (iii) CXL.mem which allows a device attached memory tobecome part of the shared system memory space. The CPU can generatecacheable requests to such a device memory.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIGS. 1A and 1B are block diagrams illustrating a generic vectorfriendly instruction format and instruction templates thereof accordingto embodiments of the invention;

FIGS. 2A-C are block diagrams illustrating an exemplary VEX instructionformat according to embodiments of the invention;

FIG. 3 is a block diagram of a register architecture according to oneembodiment of the invention; and

FIG. 4A is a block diagram illustrating both an exemplary in-orderfetch, decode, retire pipeline and an exemplary register renaming,out-of-order issue/execution pipeline according to embodiments of theinvention;

FIG. 4B is a block diagram illustrating both an exemplary embodiment ofan in-order fetch, decode, retire core and an exemplary registerrenaming, out-of-order issue/execution architecture core to be includedin a processor according to embodiments of the invention;

FIG. 5A is a block diagram of a single processor core, along with itsconnection to an on-die interconnect network;

FIG. 5B illustrates an expanded view of part of the processor core inFIG. 5A according to embodiments of the invention;

FIG. 6 is a block diagram of a single core processor and a multicoreprocessor with integrated memory controller and graphics according toembodiments of the invention;

FIG. 7 illustrates a block diagram of a system in accordance with oneembodiment of the present invention;

FIG. 8 illustrates a block diagram of a second system in accordance withan embodiment of the present invention;

FIG. 9 illustrates a block diagram of a third system in accordance withan embodiment of the present invention;

FIG. 10 illustrates a block diagram of a system on a chip (SoC) inaccordance with an embodiment of the present invention;

FIG. 11 illustrates a block diagram contrasting the use of a softwareinstruction converter to convert binary instructions in a sourceinstruction set to binary instructions in a target instruction setaccording to embodiments of the invention;

FIGS. 12A-B illustrate different embodiments for a hybrid coherencytracker;

FIG. 13 illustrates a sequence of transactions and a method inaccordance with one embodiment of the invention;

FIG. 14 illustrates a sequence of transactions and a method inaccordance with one embodiment of the invention; and

FIG. 15 illustrates a sequence of transactions and a method inaccordance with one embodiment of the invention.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

Exemplary Processor Architectures, Instruction Formats, and Data Types

An instruction set includes one or more instruction formats. A giveninstruction format defines various fields (number of bits, location ofbits) to specify, among other things, the operation to be performed(opcode) and the operand(s) on which that operation is to be performed.Some instruction formats are further broken down though the definitionof instruction templates (or subformats). For example, the instructiontemplates of a given instruction format may be defined to have differentsubsets of the instruction format's fields (the included fields aretypically in the same order, but at least some have different bitpositions because there are less fields included) and/or defined to havea given field interpreted differently. Thus, each instruction of an ISAis expressed using a given instruction format (and, if defined, in agiven one of the instruction templates of that instruction format) andincludes fields for specifying the operation and the operands. Forexample, an exemplary ADD instruction has a specific opcode and aninstruction format that includes an opcode field to specify that opcodeand operand fields to select operands (source1/destination and source2);and an occurrence of this ADD instruction in an instruction stream willhave specific contents in the operand fields that select specificoperands.

Embodiments of the instruction(s) described herein may be embodied indifferent formats. Additionally, exemplary systems, architectures, andpipelines are detailed below. Embodiments of the instruction(s) may beexecuted on such systems, architectures, and pipelines, but are notlimited to those detailed.

Generic Vector Friendly Instruction Format

A vector friendly instruction format is an instruction format that issuited for vector instructions (e.g., there are certain fields specificto vector operations). While embodiments are described in which bothvector and scalar operations are supported through the vector friendlyinstruction format, alternative embodiments use only vector operationsthe vector friendly instruction format.

FIGS. 1A-1B are block diagrams illustrating a generic vector friendlyinstruction format and instruction templates thereof according toembodiments of the invention. FIG. 1A is a block diagram illustrating ageneric vector friendly instruction format and class A instructiontemplates thereof according to embodiments of the invention; while FIG.1B is a block diagram illustrating the generic vector friendlyinstruction format and class B instruction templates thereof accordingto embodiments of the invention. Specifically, a generic vector friendlyinstruction format 100 for which are defined class A and class Binstruction templates, both of which include no memory access 105instruction templates and memory access 120 instruction templates. Theterm generic in the context of the vector friendly instruction formatrefers to the instruction format not being tied to any specificinstruction set.

While embodiments of the invention will be described in which the vectorfriendly instruction format supports the following: a 64 byte vectoroperand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) dataelement widths (or sizes) (and thus, a 64 byte vector consists of either16 doubleword-size elements or alternatively, 8 quadword-size elements);a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit(1 byte) data element widths (or sizes); a 32 byte vector operand length(or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8bit (1 byte) data element widths (or sizes); and a 16 byte vectoroperand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit(2 byte), or 8 bit (1 byte) data element widths (or sizes); alternativeembodiments may support more, less and/or different vector operand sizes(e.g., 256 byte vector operands) with more, less, or different dataelement widths (e.g., 128 bit (16 byte) data element widths).

The class A instruction templates in FIG. 1A include: 1) within the nomemory access 105 instruction templates there is shown a no memoryaccess, full round control type operation 110 instruction template and ano memory access, data transform type operation 115 instructiontemplate; and 2) within the memory access 120 instruction templatesthere is shown a memory access, temporal 125 instruction template and amemory access, non-temporal 130 instruction template. The class Binstruction templates in FIG. 1B include: 1) within the no memory access105 instruction templates there is shown a no memory access, write maskcontrol, partial round control type operation 112 instruction templateand a no memory access, write mask control, vsize type operation 117instruction template; and 2) within the memory access 120 instructiontemplates there is shown a memory access, write mask control 127instruction template.

The generic vector friendly instruction format 100 includes thefollowing fields listed below in the order illustrated in FIGS. 1A-1B.

Format field 140—a specific value (an instruction format identifiervalue) in this field uniquely identifies the vector friendly instructionformat, and thus occurrences of instructions in the vector friendlyinstruction format in instruction streams. As such, this field isoptional in the sense that it is not needed for an instruction set thathas only the generic vector friendly instruction format.

Base operation field 142—its content distinguishes different baseoperations.

Register index field 144—its content, directly or through addressgeneration, specifies the locations of the source and destinationoperands, be they in registers or in memory. These include a sufficientnumber of bits to select N registers from a P×Q (e.g. 32×512, 16×128,32×1024, 64×1024) register file. While in one embodiment N may be up tothree sources and one destination register, alternative embodiments maysupport more or less sources and destination registers (e.g., maysupport up to two sources where one of these sources also acts as thedestination, may support up to three sources where one of these sourcesalso acts as the destination, may support up to two sources and onedestination).

Modifier field 146—its content distinguishes occurrences of instructionsin the generic vector instruction format that specify memory access fromthose that do not; that is, between no memory access 105 instructiontemplates and memory access 120 instruction templates. Memory accessoperations read and/or write to the memory hierarchy (in some casesspecifying the source and/or destination addresses using values inregisters), while non-memory access operations do not (e.g., the sourceand destinations are registers). While in one embodiment this field alsoselects between three different ways to perform memory addresscalculations, alternative embodiments may support more, less, ordifferent ways to perform memory address calculations.

Augmentation operation field 150—its content distinguishes which one ofa variety of different operations to be performed in addition to thebase operation. This field is context specific. In one embodiment of theinvention, this field is divided into a class field 168, an alpha field152, and a beta field 154. The augmentation operation field 150 allowscommon groups of operations to be performed in a single instructionrather than 2, 3, or 4 instructions.

Scale field 160—its content allows for the scaling of the index field'scontent for memory address generation (e.g., for address generation thatuses 2^(scale)*index+base).

Displacement Field 162A—its content is used as part of memory addressgeneration (e.g., for address generation that uses2^(scale)*index+base+displacement).

Displacement Factor Field 1628 (note that the juxtaposition ofdisplacement field 162A directly over displacement factor field 1628indicates one or the other is used)—its content is used as part ofaddress generation; it specifies a displacement factor that is to bescaled by the size of a memory access (N)—where N is the number of bytesin the memory access (e.g., for address generation that uses2^(scale)*index+base+scaled displacement). Redundant low-order bits areignored and hence, the displacement factor field's content is multipliedby the memory operands total size (N) in order to generate the finaldisplacement to be used in calculating an effective address. The valueof N is determined by the processor hardware at runtime based on thefull opcode field 174 (described later herein) and the data manipulationfield 154C. The displacement field 162A and the displacement factorfield 162B are optional in the sense that they are not used for the nomemory access 105 instruction templates and/or different embodiments mayimplement only one or none of the two.

Data element width field 164—its content distinguishes which one of anumber of data element widths is to be used (in some embodiments for allinstructions; in other embodiments for only some of the instructions).This field is optional in the sense that it is not needed if only onedata element width is supported and/or data element widths are supportedusing some aspect of the opcodes.

Write mask field 170—its content controls, on a per data elementposition basis, whether that data element position in the destinationvector operand reflects the result of the base operation andaugmentation operation. Class A instruction templates supportmerging-writemasking, while class B instruction templates support bothmerging- and zeroing-writemasking. When merging, vector masks allow anyset of elements in the destination to be protected from updates duringthe execution of any operation (specified by the base operation and theaugmentation operation); in other one embodiment, preserving the oldvalue of each element of the destination where the corresponding maskbit has a 0. In contrast, when zeroing vector masks allow any set ofelements in the destination to be zeroed during the execution of anyoperation (specified by the base operation and the augmentationoperation); in one embodiment, an element of the destination is set to 0when the corresponding mask bit has a 0 value. A subset of thisfunctionality is the ability to control the vector length of theoperation being performed (that is, the span of elements being modified,from the first to the last one); however, it is not necessary that theelements that are modified be consecutive. Thus, the write mask field170 allows for partial vector operations, including loads, stores,arithmetic, logical, etc. While embodiments of the invention aredescribed in which the write mask field's 170 content selects one of anumber of write mask registers that contains the write mask to be used(and thus the write mask field's 170 content indirectly identifies thatmasking to be performed), alternative embodiments instead or additionalallow the mask write field's 170 content to directly specify the maskingto be performed.

Immediate field 172—its content allows for the specification of animmediate. This field is optional in the sense that is it not present inan implementation of the generic vector friendly format that does notsupport immediate and it is not present in instructions that do not usean immediate.

Class field 168—its content distinguishes between different classes ofinstructions. With reference to FIGS. 1A-B, the contents of this fieldselect between class A and class B instructions. In FIGS. 1A-B, roundedcorner squares are used to indicate a specific value is present in afield (e.g., class A 168A and class B 168B for the class field 168respectively in FIGS. 1A-B).

Instruction Templates of Class A

In the case of the non-memory access 105 instruction templates of classA, the alpha field 152 is interpreted as an RS field 152A, whose contentdistinguishes which one of the different augmentation operation typesare to be performed (e.g., round 152A.1 and data transform 152A.2 arerespectively specified for the no memory access, round type operation110 and the no memory access, data transform type operation 115instruction templates), while the beta field 154 distinguishes which ofthe operations of the specified type is to be performed. In the nomemory access 105 instruction templates, the scale field 160, thedisplacement field 162A, and the displacement scale filed 162B are notpresent.

No-Memory Access Instruction Templates—Full Round Control Type Operation

In the no memory access full round control type operation 110instruction template, the beta field 154 is interpreted as a roundcontrol field 154A, whose content(s) provide static rounding. While inthe described embodiments of the invention the round control field 154Aincludes a suppress all floating point exceptions (SAE) field 156 and around operation control field 158, alternative embodiments may supportmay encode both these concepts into the same field or only have one orthe other of these concepts/fields (e.g., may have only the roundoperation control field 158).

SAE field 156—its content distinguishes whether or not to disable theexception event reporting; when the SAE field's 156 content indicatessuppression is enabled, a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler.

Round operation control field 158—its content distinguishes which one ofa group of rounding operations to perform (e.g., Round-up, Round-down,Round-towards-zero and Round-to-nearest). Thus, the round operationcontrol field 158 allows for the changing of the rounding mode on a perinstruction basis. In one embodiment of the invention where a processorincludes a control register for specifying rounding modes, the roundoperation control field's 150 content overrides that register value.

No Memory Access Instruction Templates—Data Transform Type Operation

In the no memory access data transform type operation 115 instructiontemplate, the beta field 154 is interpreted as a data transform field1546, whose content distinguishes which one of a number of datatransforms is to be performed (e.g., no data transform, swizzle,broadcast).

In the case of a memory access 120 instruction template of class A, thealpha field 152 is interpreted as an eviction hint field 1526, whosecontent distinguishes which one of the eviction hints is to be used (inFIG. 1A, temporal 152B.1 and non-temporal 152B.2 are respectivelyspecified for the memory access, temporal 125 instruction template andthe memory access, non-temporal 130 instruction template), while thebeta field 154 is interpreted as a data manipulation field 154C, whosecontent distinguishes which one of a number of data manipulationoperations (also known as primitives) is to be performed (e.g., nomanipulation; broadcast; up conversion of a source; and down conversionof a destination). The memory access 120 instruction templates includethe scale field 160, and optionally the displacement field 162A or thedisplacement scale field 162B.

Vector memory instructions perform vector loads from and vector storesto memory, with conversion support. As with regular vector instructions,vector memory instructions transfer data from/to memory in a dataelement-wise fashion, with the elements that are actually transferred isdictated by the contents of the vector mask that is selected as thewrite mask.

Memory Access Instruction Templates—Temporal

Temporal data is data likely to be reused soon enough to benefit fromcaching. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Memory Access Instruction Templates—Non-Temporal

Non-temporal data is data unlikely to be reused soon enough to benefitfrom caching in the 1st-level cache and should be given priority foreviction. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field 152is interpreted as a write mask control (Z) field 152C, whose contentdistinguishes whether the write masking controlled by the write maskfield 170 should be a merging or a zeroing.

In the case of the non-memory access 105 instruction templates of classB, part of the beta field 154 is interpreted as an RL field 157A, whosecontent distinguishes which one of the different augmentation operationtypes are to be performed (e.g., round 157A.1 and vector length (VSIZE)157A.2 are respectively specified for the no memory access, write maskcontrol, partial round control type operation 112 instruction templateand the no memory access, write mask control, VSIZE type operation 117instruction template), while the rest of the beta field 154distinguishes which of the operations of the specified type is to beperformed. In the no memory access 105 instruction templates, the scalefield 160, the displacement field 162A, and the displacement scale filed162B are not present.

In the no memory access, write mask control, partial round control typeoperation 110 instruction template, the rest of the beta field 154 isinterpreted as a round operation field 159A and exception eventreporting is disabled (a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler).

Round operation control field 159A—just as round operation control field158, its content distinguishes which one of a group of roundingoperations to perform (e.g., Round-up, Round-down, Round-towards-zeroand Round-to-nearest). Thus, the round operation control field 159Aallows for the changing of the rounding mode on a per instruction basis.In one embodiment of the invention where a processor includes a controlregister for specifying rounding modes, the round operation controlfield's 150 content overrides that register value.

In the no memory access, write mask control, VSIZE type operation 117instruction template, the rest of the beta field 154 is interpreted as avector length field 159B, whose content distinguishes which one of anumber of data vector lengths is to be performed on (e.g., 128, 256, or512 byte).

In the case of a memory access 120 instruction template of class B, partof the beta field 154 is interpreted as a broadcast field 157B, whosecontent distinguishes whether or not the broadcast type datamanipulation operation is to be performed, while the rest of the betafield 154 is interpreted the vector length field 159B. The memory access120 instruction templates include the scale field 160, and optionallythe displacement field 162A or the displacement scale field 162B.

With regard to the generic vector friendly instruction format 100, afull opcode field 174 is shown including the format field 140, the baseoperation field 142, and the data element width field 164. While oneembodiment is shown where the full opcode field 174 includes all ofthese fields, the full opcode field 174 includes less than all of thesefields in embodiments that do not support all of them. The full opcodefield 174 provides the operation code (opcode).

The augmentation operation field 150, the data element width field 164,and the write mask field 170 allow these features to be specified on aper instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field createtyped instructions in that they allow the mask to be applied based ondifferent data element widths.

The various instruction templates found within class A and class B arebeneficial in different situations. In some embodiments of theinvention, different processors or different cores within a processormay support only class A, only class B, or both classes. For instance, ahigh performance general purpose out-of-order core intended forgeneral-purpose computing may support only class B, a core intendedprimarily for graphics and/or scientific (throughput) computing maysupport only class A, and a core intended for both may support both (ofcourse, a core that has some mix of templates and instructions from bothclasses but not all templates and instructions from both classes iswithin the purview of the invention). Also, a single processor mayinclude multiple cores, all of which support the same class or in whichdifferent cores support different class. For instance, in a processorwith separate graphics and general purpose cores, one of the graphicscores intended primarily for graphics and/or scientific computing maysupport only class A, while one or more of the general purpose cores maybe high performance general purpose cores with out of order executionand register renaming intended for general-purpose computing thatsupport only class B. Another processor that does not have a separategraphics core, may include one more general purpose in-order orout-of-order cores that support both class A and class B. Of course,features from one class may also be implement in the other class indifferent embodiments of the invention. Programs written in a high levellanguage would be put (e.g., just in time compiled or staticallycompiled) into an variety of different executable forms, including: 1) aform having only instructions of the class(es) supported by the targetprocessor for execution; or 2) a form having alternative routineswritten using different combinations of the instructions of all classesand having control flow code that selects the routines to execute basedon the instructions supported by the processor which is currentlyexecuting the code.

VEX Instruction Format

VEX encoding allows instructions to have more than two operands, andallows SIMD vector registers to be longer than 28 bits. The use of a VEXprefix provides for three-operand (or more) syntax. For example,previous two-operand instructions performed operations such as A=A+B,which overwrites a source operand. The use of a VEX prefix enablesoperands to perform nondestructive operations such as A=B+C.

FIG. 2A illustrates an exemplary AVX instruction format including a VEXprefix 202, real opcode field 230, Mod R/M byte 240, SIB byte 250,displacement field 262, and IMM8 272. FIG. 2B illustrates which fieldsfrom FIG. 2A make up a full opcode field 274 and a base operation field241. FIG. 2C illustrates which fields from FIG. 2A make up a registerindex field 244.

VEX Prefix (Bytes 0-2) 202 is encoded in a three-byte form. The firstbyte is the Format Field 290 (VEX Byte 0, bits [7:0]), which contains anexplicit C4 byte value (the unique value used for distinguishing the C4instruction format). The second-third bytes (VEX Bytes 1-2) include anumber of bit fields providing specific capability. Specifically, REXfield 205 (VEX Byte 1, bits [7-5]) consists of a VEX.R bit field (VEXByte 1, bit [7]—R), VEX.X bit field (VEX byte 1, bit [6]—X), and VEX.Bbit field (VEX byte 1, bit[5]—B). Other fields of the instructionsencode the lower three bits of the register indexes as is known in theart (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed byadding VEX.R, VEX.X, and VEX.B. Opcode map field 215 (VEX byte 1, bits[4:0]—mmmmm) includes content to encode an implied leading opcode byte.W Field 264 (VEX byte 2, bit [7]—W)—is represented by the notationVEX.W, and provides different functions depending on the instruction.The role of VEX.vvvv 220 (VEX Byte 2, bits [6:3]—vvvv) may include thefollowing: 1) VEX.vvvv encodes the first source register operand,specified in inverted (1s complement) form and is valid for instructionswith 2 or more source operands; 2) VEX.vvvv encodes the destinationregister operand, specified in 1s complement form for certain vectorshifts; or 3) VEX.vvvv does not encode any operand, the field isreserved and should contain 1111b. If VEX.L 268 Size field (VEX byte 2,bit [2]—L)=0, it indicates 28 bit vector; if VEX.L=1, it indicates 256bit vector. Prefix encoding field 225 (VEX byte 2, bits [1:0]—pp)provides additional bits for the base operation field 241.

Real Opcode Field 230 (Byte 3) is also known as the opcode byte. Part ofthe opcode is specified in this field.

MOD R/M Field 240 (Byte 4) includes MOD field 242 (bits [7-6]), Regfield 244 (bits [5-3]), and R/M field 246 (bits [2-0]). The role of Regfield 244 may include the following: encoding either the destinationregister operand or a source register operand (the rrr of Rrrr), or betreated as an opcode extension and not used to encode any instructionoperand. The role of R/M field 246 may include the following: encodingthe instruction operand that references a memory address, or encodingeither the destination register operand or a source register operand.

Scale, Index, Base (SIB)—The content of Scale field 250 (Byte 5)includes SS252 (bits [7-6]), which is used for memory addressgeneration. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256(bits [2-0]) have been previously referred to with regard to theregister indexes Xxxx and Bbbb.

The Displacement Field 262 and the immediate field (IMM8) 272 containdata.

Exemplary Register Architecture

FIG. 3 is a block diagram of a register architecture 300 according toone embodiment of the invention. In the embodiment illustrated, thereare 32 vector registers 310 that are 512 bits wide; these registers arereferenced as zmm0 through zmm31. The lower order 256 bits of the lower6 zmm registers are overlaid on registers ymm0-15. The lower order 128bits of the lower 6 zmm registers (the lower order 128 bits of the ymmregisters) are overlaid on registers xmm0-15.

General-purpose registers 325—in the embodiment illustrated, there aresixteen 64-bit general-purpose registers that are used along with theexisting x86 addressing modes to address memory operands. Theseregisters are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI,RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 345, on which isaliased the MMX packed integer flat register file 350—in the embodimentillustrated, the x87 stack is an eight-element stack used to performscalar floating-point operations on 32/64/80-bit floating point datausing the x87 instruction set extension; while the MMX registers areused to perform operations on 64-bit packed integer data, as well as tohold operands for some operations performed between the MMX and XMMregisters.

Alternative embodiments of the invention may use wider or narrowerregisters. Additionally, alternative embodiments of the invention mayuse more, less, or different register files and registers.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for differentpurposes, and in different processors. For instance, implementations ofsuch cores may include: 1) a general purpose in-order core intended forgeneral-purpose computing; 2) a high performance general purposeout-of-order core intended for general-purpose computing; 3) a specialpurpose core intended primarily for graphics and/or scientific(throughput) computing. Implementations of different processors mayinclude: 1) a CPU including one or more general purpose in-order coresintended for general-purpose computing and/or one or more generalpurpose out-of-order cores intended for general-purpose computing; and2) a coprocessor including one or more special purpose cores intendedprimarily for graphics and/or scientific (throughput). Such differentprocessors lead to different computer system architectures, which mayinclude: 1) the coprocessor on a separate chip from the CPU; 2) thecoprocessor on a separate die in the same package as a CPU; 3) thecoprocessor on the same die as a CPU (in which case, such a coprocessoris sometimes referred to as special purpose logic, such as integratedgraphics and/or scientific (throughput) logic, or as special purposecores); and 4) a system on a chip that may include on the same die thedescribed CPU (sometimes referred to as the application core(s) orapplication processor(s)), the above described coprocessor, andadditional functionality. Exemplary core architectures are describednext, followed by descriptions of exemplary processors and computerarchitectures. Detailed herein are circuits (units) that compriseexemplary cores, processors, etc.

Exemplary Core Architectures

FIG. 4A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention. FIG.4B is a block diagram illustrating both an exemplary embodiment of anin-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention. The solid linedboxes in FIGS. 4A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 4A, a processor pipeline 400 includes a fetch stage 402, alength decode stage 404, a decode stage 406, an allocation stage 408, arenaming stage 410, a scheduling (also known as a dispatch or issue)stage 412, a register read/memory read stage 414, an execute stage 416,a write back/memory write stage 418, an exception handling stage 422,and a commit stage 424.

FIG. 4B shows processor core 490 including a front end unit 430 coupledto an execution engine unit 450, and both are coupled to a memory unit470. The core 490 may be a reduced instruction set computing (RISC)core, a complex instruction set computing (CISC) core, a very longinstruction word (VLIW) core, or a hybrid or alternative core type. Asyet another option, the core 490 may be a special-purpose core, such as,for example, a network or communication core, compression engine,coprocessor core, general purpose computing graphics processing unit(GPGPU) core, graphics core, or the like.

The front end unit 430 includes a branch prediction unit 432 coupled toan instruction cache unit 434, which is coupled to an instructiontranslation lookaside buffer (TLB) 436, which is coupled to aninstruction fetch unit 438, which is coupled to a decode unit 440. Thedecode unit 440 (or decoder) may decode instructions, and generate as anoutput one or more micro-operations, micro-code entry points,microinstructions, other instructions, or other control signals, whichare decoded from, or which otherwise reflect, or are derived from, theoriginal instructions. The decode unit 440 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. In one embodiment, the core 490 includes a microcode ROM or othermedium that stores microcode for certain macroinstructions (e.g., indecode unit 440 or otherwise within the front end unit 430). The decodeunit 440 is coupled to a rename/allocator unit 452 in the executionengine unit 450.

The execution engine unit 450 includes the rename/allocator unit 452coupled to a retirement unit 454 and a set of one or more schedulerunit(s) 456. The scheduler unit(s) 456 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 456 is coupled to thephysical register file(s) unit(s) 458. Each of the physical registerfile(s) units 458 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit458 comprises a vector registers unit and a scalar registers unit. Theseregister units may provide architectural vector registers, vector maskregisters, and general purpose registers. The physical register file(s)unit(s) 458 is overlapped by the retirement unit 454 to illustratevarious ways in which register renaming and out-of-order execution maybe implemented (e.g., using a reorder buffer(s) and a retirementregister file(s); using a future file(s), a history buffer(s), and aretirement register file(s); using a register maps and a pool ofregisters; etc.). The retirement unit 454 and the physical registerfile(s) unit(s) 458 are coupled to the execution cluster(s) 460. Theexecution cluster(s) 460 includes a set of one or more execution units462 and a set of one or more memory access units 464. The executionunits 462 may perform various operations (e.g., shifts, addition,subtraction, multiplication) and on various types of data (e.g., scalarfloating point, packed integer, packed floating point, vector integer,vector floating point). While some embodiments may include a number ofexecution units dedicated to specific functions or sets of functions,other embodiments may include only one execution unit or multipleexecution units that all perform all functions. The scheduler unit(s)456, physical register file(s) unit(s) 458, and execution cluster(s) 460are shown as being possibly plural because certain embodiments createseparate pipelines for certain types of data/operations (e.g., a scalarinteger pipeline, a scalar floating point/packed integer/packed floatingpoint/vector integer/vector floating point pipeline, and/or a memoryaccess pipeline that each have their own scheduler unit, physicalregister file(s) unit, and/or execution cluster—and in the case of aseparate memory access pipeline, certain embodiments are implemented inwhich only the execution cluster of this pipeline has the memory accessunit(s) 464). It should also be understood that where separate pipelinesare used, one or more of these pipelines may be out-of-orderissue/execution and the rest in-order.

The set of memory access units 464 is coupled to the memory unit 470,which includes a data TLB unit 472 coupled to a data cache unit 474coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment,the memory access units 464 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 472 in the memory unit 470. The instruction cache unit 434 isfurther coupled to a level 2 (L2) cache unit 476 in the memory unit 470.The L2 cache unit 476 is coupled to one or more other levels of cacheand eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 400 asfollows: 1) the instruction fetch 438 performs the fetch and lengthdecoding stages 402 and 404; 2) the decode unit 440 performs the decodestage 406; 3) the rename/allocator unit 452 performs the allocationstage 408 and renaming stage 410; 4) the scheduler unit(s) 456 performsthe schedule stage 412; 5) the physical register file(s) unit(s) 458 andthe memory unit 470 perform the register read/memory read stage 414; theexecution cluster 460 perform the execute stage 416; 6) the memory unit470 and the physical register file(s) unit(s) 458 perform the writeback/memory write stage 418; 7) various units may be involved in theexception handling stage 422; and 8) the retirement unit 454 and thephysical register file(s) unit(s) 458 perform the commit stage 424.

The core 490 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 490includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2), thereby allowing the operations used by many multimediaapplications to be performed using packed data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units434/474 and a shared L2 cache unit 476, alternative embodiments may havea single internal cache for both instructions and data, such as, forexample, a Level 1 (L1) internal cache, or multiple levels of internalcache. In some embodiments, the system may include a combination of aninternal cache and an external cache that is external to the core and/orthe processor. Alternatively, all of the cache may be external to thecore and/or the processor.

Specific Exemplary in-Order Core Architecture

FIGS. 5A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 5A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 502 and with its localsubset of the Level 2 (L2) cache 504, according to embodiments of theinvention. In one embodiment, an instruction decoder 500 supports thex86 instruction set with a packed data instruction set extension. An L1cache 506 allows low-latency accesses to cache memory into the scalarand vector units. While in one embodiment (to simplify the design), ascalar unit 508 and a vector unit 510 use separate register sets(respectively, scalar registers 512 and vector registers 514) and datatransferred between them is written to memory and then read back in froma level 1 (L1) cache 506, alternative embodiments of the invention mayuse a different approach (e.g., use a single register set or include acommunication path that allow data to be transferred between the tworegister files without being written and read back).

The local subset of the L2 cache 504 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 504. Data read by a processor core is stored in its L2 cachesubset 504 and can be accessed quickly, in parallel with other processorcores accessing their own local L2 cache subsets. Data written by aprocessor core is stored in its own L2 cache subset 504 and is flushedfrom other subsets, if necessary. The ring network ensures coherency forshared data. The ring network is bi-directional to allow agents such asprocessor cores, L2 caches and other logic blocks to communicate witheach other within the chip. Each ring data-path is 1024-bits wide perdirection in some embodiments.

FIG. 5B is an expanded view of part of the processor core in FIG. 5Aaccording to embodiments of the invention. FIG. 5B includes an L1 datacache 506A part of the L1 cache 504, as well as more detail regardingthe vector unit 510 and the vector registers 514. Specifically, thevector unit 510 is a 6-wide vector processing unit (VPU) (see the16-wide ALU 528), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 520, numericconversion with numeric convert units 522A-B, and replication withreplication unit 524 on the memory input.

Processor with Integrated Memory Controller and Graphics

FIG. 6 is a block diagram of a processor 600 that may have more than onecore, may have an integrated memory controller, and may have integratedgraphics according to embodiments of the invention. The solid linedboxes in FIG. 6 illustrate a processor 600 with a single core 602A, asystem agent 610, a set of one or more bus controller units 616, whilethe optional addition of the dashed lined boxes illustrates analternative processor 600 with multiple cores 602A-N, a set of one ormore integrated memory controller unit(s) 614 in the system agent unit610, and special purpose logic 608.

Thus, different implementations of the processor 600 may include: 1) aCPU with the special purpose logic 608 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 602A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 602A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores602A-N being a large number of general purpose in-order cores. Thus, theprocessor 600 may be a general-purpose processor, coprocessor orspecial-purpose processor, such as, for example, a network orcommunication processor, compression engine, graphics processor, GPGPU(general purpose graphics processing unit), a high-throughput manyintegrated core (MIC) coprocessor (including 30 or more cores), embeddedprocessor, or the like. The processor may be implemented on one or morechips. The processor 600 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within thecores 604A-N, a set or one or more shared cache units 606, and externalmemory (not shown) coupled to the set of integrated memory controllerunits 614. The set of shared cache units 606 may include one or moremid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), orother levels of cache, a last level cache (LLC), and/or combinationsthereof. While in one embodiment a ring based interconnect unit 612interconnects the integrated graphics logic 608, the set of shared cacheunits 606, and the system agent unit 610/integrated memory controllerunit(s) 614, alternative embodiments may use any number of well-knowntechniques for interconnecting such units. In one embodiment, coherencyis maintained between one or more cache units 606 and cores 602-A-N.

In some embodiments, one or more of the cores 602A-N are capable ofmulti-threading. The system agent 610 includes those componentscoordinating and operating cores 602A-N. The system agent unit 610 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 602A-N and the integrated graphics logic 608.The display unit is for driving one or more externally connecteddisplays.

The cores 602A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 602A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

Exemplary Computer Architectures

FIGS. 7-10 are block diagrams of exemplary computer architectures. Othersystem designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 7, shown is a block diagram of a system 700 inaccordance with one embodiment of the present invention. The system 700may include one or more processors 710, 715, which are coupled to acontroller hub 720. In one embodiment, the controller hub 720 includes agraphics memory controller hub (GMCH) 790 and an Input/Output Hub (IOH)750 (which may be on separate chips); the GMCH 790 includes memory andgraphics controllers to which are coupled memory 740 and a coprocessor745; the IOH 750 is couples input/output (I/O) devices 760 to the GMCH790. Alternatively, one or both of the memory and graphics controllersare integrated within the processor (as described herein), the memory740 and the coprocessor 745 are coupled directly to the processor 710,and the controller hub 720 in a single chip with the IOH 750.

The optional nature of additional processors 715 is denoted in FIG. 7with broken lines. Each processor 710, 715 may include one or more ofthe processing cores described herein and may be some version of theprocessor 600.

The memory 740 may be, for example, dynamic random access memory (DRAM),phase change memory (PCM), or a combination of the two. For at least oneembodiment, the controller hub 720 communicates with the processor(s)710, 715 via a multi-drop bus, such as a frontside bus (FSB),point-to-point interface, or similar connection 795.

In one embodiment, the coprocessor 745 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 720may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources710, 7155 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 710 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 710recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 745. Accordingly, the processor710 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 745. Coprocessor(s) 745 accept and executethe received coprocessor instructions.

Referring now to FIG. 8, shown is a block diagram of a first morespecific exemplary system 800 in accordance with an embodiment of thepresent invention. As shown in FIG. 8, multiprocessor system 800 is apoint-to-point interconnect system, and includes a first processor 870and a second processor 880 coupled via a point-to-point interconnect850. Each of processors 870 and 880 may be some version of the processor600. In one embodiment of the invention, processors 870 and 880 arerespectively processors 710 and 715, while coprocessor 838 iscoprocessor 745. In another embodiment, processors 870 and 880 arerespectively processor 710 coprocessor 745.

Processors 870 and 880 are shown including integrated memory controller(IMC) units 872 and 882, respectively. Processor 870 also includes aspart of its bus controller units point-to-point (P-P) interfaces 876 and878; similarly, second processor 880 includes P-P interfaces 886 and888. Processors 870, 880 may exchange information via a point-to-point(P-P) interface 850 using P-P interface circuits 878, 888. As shown inFIG. 8, IMCs 872 and 882 couple the processors to respective memories,namely a memory 832 and a memory 834, which may be portions of mainmemory locally attached to the respective processors.

Processors 870, 880 may each exchange information with a chipset 890 viaindividual P-P interfaces 852, 854 using point to point interfacecircuits 876, 894, 886, 898. Chipset 890 may optionally exchangeinformation with the coprocessor 838 via a high-performance interface892. In one embodiment, the coprocessor 838 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 890 may be coupled to a first bus 816 via an interface 896. Inone embodiment, first bus 816 may be a Peripheral Component Interconnect(PCI) bus, or a bus such as a PCI Express bus or another I/Ointerconnect bus, although the scope of the present invention is not solimited.

As shown in FIG. 8, various I/O devices 814 may be coupled to first bus816, along with a bus bridge 818 which couples first bus 816 to a secondbus 820. In one embodiment, one or more additional processor(s) 815,such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 816. In one embodiment, second bus820 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 820 including, for example, a keyboard and/or mouse 822,communication devices 827 and a storage unit 828 such as a disk drive orother mass storage device which may include instructions/code and data830, in one embodiment. Further, an audio I/O 824 may be coupled to thesecond bus 816. Note that other architectures are possible. For example,instead of the point-to-point architecture of FIG. 8, a system mayimplement a multi-drop bus or other such architecture.

Referring now to FIG. 9, shown is a block diagram of a second morespecific exemplary system 900 in accordance with an embodiment of thepresent invention. Like elements in FIGS. 8 and 9 bear like referencenumerals, and certain aspects of FIG. 8 have been omitted from FIG. 9 inorder to avoid obscuring other aspects of FIG. 9.

FIG. 9 illustrates that the processors 870, 880 may include integratedmemory and I/O control logic (“CL”) 972 and 982, respectively. Thus, theCL 972, 982 include integrated memory controller units and include I/Ocontrol logic. FIG. 9 illustrates that not only are the memories 832,834 coupled to the CL 872, 882, but also that I/O devices 914 are alsocoupled to the control logic 872, 882. Legacy I/O devices 915 arecoupled to the chipset 890.

Referring now to FIG. 10, shown is a block diagram of a SoC 1000 inaccordance with an embodiment of the present invention. Similar elementsin FIG. 6 bear like reference numerals. Also, dashed lined boxes areoptional features on more advanced SoCs. In FIG. 10, an interconnectunit(s) 1002 is coupled to: an application processor 1010 which includesa set of one or more cores 102A-N, cache units 604A-N, and shared cacheunit(s) 606; a system agent unit 610; a bus controller unit(s) 616; anintegrated memory controller unit(s) 614; a set or one or morecoprocessors 1020 which may include integrated graphics logic, an imageprocessor, an audio processor, and a video processor; an static randomaccess memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032;and a display unit 1040 for coupling to one or more external displays.In one embodiment, the coprocessor(s) 1020 include a special-purposeprocessor, such as, for example, a network or communication processor,compression engine, GPGPU, a high-throughput MIC processor, embeddedprocessor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented inhardware, software, firmware, or a combination of such implementationapproaches. Embodiments of the invention may be implemented as computerprograms or program code executing on programmable systems comprising atleast one processor, a storage system (including volatile andnon-volatile memory and/or storage elements), at least one input device,and at least one output device.

Program code, such as code 830 illustrated in FIG. 8, may be applied toinput instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

Emulation (Including Binary Translation, Code Morphing, Etc.)

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 11 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 11 shows a program in ahigh level language 1102 may be compiled using an first compiler 1104 togenerate a first binary code (e.g., x86) 1106 that may be nativelyexecuted by a processor with at least one first instruction set core1116. In some embodiments, the processor with at least one firstinstruction set core 1116 represents any processor that can performsubstantially the same functions as an Intel processor with at least onex86 instruction set core by compatibly executing or otherwise processing(1) a substantial portion of the instruction set of the Intel x86instruction set core or (2) object code versions of applications orother software targeted to run on an Intel processor with at least onex86 instruction set core, in order to achieve substantially the sameresult as an Intel processor with at least one x86 instruction set core.The first compiler 1104 represents a compiler that is operable togenerate binary code of the first instruction set 1106 (e.g., objectcode) that can, with or without additional linkage processing, beexecuted on the processor with at least one first instruction set core1116. Similarly, FIG. 11 shows the program in the high level language1102 may be compiled using an alternative instruction set compiler 1108to generate alternative instruction set binary code 1110 that may benatively executed by a processor without at least one first instructionset core 1114 (e.g., a processor with cores that execute the MIPSinstruction set of MIPS Technologies of Sunnyvale, Calif. and/or thatexecute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.).The instruction converter 1112 is used to convert the first binary code1106 into code that may be natively executed by the processor without anfirst instruction set core 1114. This converted code is not likely to bethe same as the alternative instruction set binary code 1110 because aninstruction converter capable of this is difficult to make; however, theconverted code will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 1112 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have a firstinstruction set processor or core to execute the first binary code 1106.

Coherency Tracking Apparatus and Method for an Attached Coprocessor orAccelerator

The Compute Express Link (CXL) is a coherent link for attachingaccelerator devices which supports three types of protocols: (i) CXL.iowhich is semantically equivalent to a PCI Express (PCIe) link; (ii)CXL.cache which allows the accelerator to generate coherent requests tohost memory; and (iii) CXL.mem which allows a device attached memory tobecome part of the shared system memory space. The CPU can generatecacheable requests to such a device memory.

A CXL.mem-compliant accelerator device implements a device coherencyengine (DCOH) to maintain a coherent view of the device memory acrossall request agents. A request agent may be any processing deviceincluding a CPU, GPU, other accelerator, or I/O device that can accessthe device memory. One implementation of DCOH implements a tracker totrack coherent copies of each cache line requested by agents, referredto herein as a “coherency tracker.”

One embodiment of the invention comprises an architecture and associatedtechniques for implementing a hybrid coherency tracker (HCT) that iscooperatively managed by different combinations of hardware andsoftware. These embodiments operate more efficiently and are lesscomplex than other implementations, resulting in less chip surface areabeing consumed. The HCT also enables flexible organization of trackingstructure.

Before describing the embodiments of the invention, an overview of threetypes of coherency trackers is provided: (1) hardware coherency trackerwith limited coverage; (2) hardware coherency tracker with fullcoverage; and (3) software coherency trackers. Embodiments of theinvention may utilize various features of these coherency trackers (asdescribed below).

Hardware Coherency Tracker with Limited Coverage

A hardware coherency tracker may implement a tag and data structure inRAM, much like a cache tag and data. The hardware coherency tracker'stag stores the address while data structure stores an indication of: (i)which request agent may have a cached copy of the line; and (ii) thestate of the line.

Allocation in and eviction out of the coherency tracker is managed byhardware. Consequently, the amount of silicon area that can be dedicatedto the tag and cache structures limits the coverage of a hardwarecoherency tracker. Once the tracker is full, any new request to allocatein the coherency tracker will evict an old entry. An eviction willsnoop-invalidate the requestors cache. A hardware coherency tracker withlimited coverage limits the amount of device memory that can be cacheresident at the requestor agents.

Hardware Coherency Tracker with Full Coverage

A full coverage system uses part of the device memory to store thecoherency tracker structure. This is also sometimes referred to as adirectory-based tracker. There are various implementations of thisarchitecture that use different organizations of the coherency trackerin memory. Some implementations store the directory information in-linewith the data, by stealing some portion of the error correction code(ECC) bits in DRAM. Other implementations reserve a region of memory,and build an in-memory database to store the directory bits. A hardwarecoherency tracker cache may be used to reduce the cost of the memorylookup.

Directory based implementations provide full coverage, at the cost ofadditional complexity and additional memory bandwidth overhead. However,directory implementations eliminate the need to snoop invalidaterequestor caches due to capacity evictions. The amount of device memorya requestor agent may cache is only limited by the requestor's cachesize.

Software Coherency Tracker

The traditional accelerator programming model presented a programmaticway for software to define explicit points at which ownership of datawas transferred between the host/CPU and accelerator agents. Forexample, OpenCL coarse-grained buffer SVM defines explicit transfer ofownership between the host/CPU and the accelerator agent (often a GPU).Accelerators designed to support such programming models need nohardware coherency tracking because software provides the guarantees.Some implementations may include an “ownership transfer engine” inhardware, that software can use to snoop invalidate caches whentransferring ownership from one agent to another. The software coherencytracker does not support concurrent access to a cache line betweenrequestors, but it significantly reduces the hardware complexity.

Embodiments of a Hybrid Coherency Tracker

In contrast to existing implementations which either rely exclusively onhardware or software, one embodiment of the invention comprises a hybridcoherency tracker (HCT) with a hardware component to manage the transferof ownership of a device address from the accelerator to the host/CPU.After the transfer, the accelerator may request access to the line tooperate in an “indirect access mode (IAM)” in which it remains untilsoftware transfers the ownership of the cache line back from thehost/CPU to the accelerator.

In one embodiment, the hybrid coherency tracker presents a fullycoherent view of the device memory at all times and is applicationtransparent (e.g., no explicit ownership transfers are required from theuser application). This embodiment simplifies the coherency trackercomplexity in the hardware and conserves memory bandwidth, because thehardware doesn't have to manage back eviction required (and potentialdeadlock) for a hardware coherency tracker with limited coverage; or amemory-backed coherency tracker (and the corresponding impact on memorybandwidth).

Moreover, certain embodiments of the hybrid coherency tracker include acoarse-grained coherency tracker indexed using an address hash. Theseembodiments do not have to implement a reverse hash function in hardwarebecause hardware does not have to snoop-evict the line from thehost/CPU.

FIG. 12A illustrates one particular embodiment comprising a processor1200 coupled to an accelerator device 1250 over a coherent interconnect1240. While the interconnect 1240 comprises a compute express link (CXL)in one embodiment, the underlying principles of the invention are notlimited to a CXL implementation. The processor 1200 may comprise aspecial purpose or general purpose host processor (e.g., a CPU) whilethe accelerator device 1250 may be any type of accelerator including,but not limited to, a graphics processor, digital signal processor, acommunication processor, a vector/tensor processor, or a morespecialized type of processor (e.g., a ray tracing accelerator).However, the underlying principles of the invention are not limited toany particular type of accelerator device 1250.

The processor 1200 comprises one or more cores 1210 for executinginstructions and processing data stored in a processor memory 1230, anaccelerator device memory 1295, and/or cached within one or more localcaches 1215. The accelerator device 1250 comprises one or moreprocessing elements 1255 for executing instructions and/or processingdata stored in an accelerator device memory 1295, the processor memory1230, and/or cached in one or more accelerator caches 1260. Theprocessor 1200 includes a memory controller 1225 to directly connect tothe processor memory 1230 and the accelerator device 1250 includes amemory controller 1226 to directly connect the accelerator device 1250to the accelerator device memory 1295.

As indicated in FIG. 12A, an address translator 1220 of the translatesvirtual memory addresses to physical memory addresses, some of whichreside in the processor memory 1230 and some of which may reside in theaccelerator device memory 1295. If the physical address points to theprocessor memory 1230, then the memory controller 1225 processes thememory request on behalf of the requesting core 1210 and (in the case ofa memory read request) stores the data in one or more cache lines of theprocessor/core cache(s) 1215.

Alternatively, if the physical address points to the accelerator devicememory 1295, then the memory controller 1225 requests the data over thecoherent interconnect 1240. The data is then copied from the acceleratordevice memory 1295 and transmitted over the coherent link 1240 to thecache(s) 1215 of the processor 1200. In one embodiment, the devicecoherency engine 1280 includes a hybrid coherency tracker 1285 to ensurethat the data shared over the coherent link 1240 is maintained in aconsistent state. For example, if the data retrieved from theaccelerator device memory 1295 and stored in the cache(s) 1215 ismodified, then the device coherency engine 1280 updates thecorresponding state in the hybrid coherency tracker 1285 to ensure thatany entity attempting to access the data sees that it has been modifiedin the processor's 1200 cache(s) 1215.

Thus, in this embodiment, the coherently attached accelerator device1250 presents the accelerator device memory 1295 as a shared systemresource, and relies on the device coherency engine 1280 and hybridcoherency tracker 1285 to ensure consistent data. In one embodiment, twoownership states are implemented by the hybrid coherency tracker 1285: afirst state indicating that the data is currently owned by theaccelerator device 1250 and a second state indicating that the data iscurrently owned by the processor 1200. In some embodiments, the hybridcoherency tracker 1285 may utilize additional states such as MSI, MESI,or MOESI (modified, owned, exclusive, shared, invalid). For simplicity,however, the examples provided below include a hybrid coherency tracker1285 with the following two ownership states which may be applied at thegranularity of cache lines, sets of cache lines, or portions of cachelines:

1) Owned by Accelerator (OBA)—For a cache line (or other data block) inthis state, the processor's cache(s) 1215 do not store a copy of thecache line. The accelerator can “directly” access the cache line fromits device memory 1295 (i.e., at the highest bandwidth and lowestlatency of access).

2) Owned by Processor (OBP)—In this state, the processor's cache(s) 1215may have a copy of the line. In one embodiment, the OBP state does notindicate what state the line is cached in, or the processor/socket inwhich it may be cached.

In one implementation, the basic operation of the device coherencyengine 1280 with hybrid coherency tracker 1285 is as follows:

Request from Processor 1200 to Device Memory 1295

1. The request misses the processor 1200 caches. The address istranslated by the address translated 1220 to the device memory 1295 andthe request is routed over coherent link 1240 to the accelerator device1250.

2. Implementations may skip a lookup in the coherency tracker 1285 forprocessor 1200 requests to device memory 1295, and assume the line to bein OBA state.

3. The device coherency tracker 1285 invokes the OBA-to-OBP state changeflow described below, adjusting the ownership state to the processor1200.

4. It accesses the device memory 1295 (for a read operation) and returnsa response back processor 1200.

Request from Accelerator Device 1250 to Device Memory 1295

1. When the request misses the accelerator caches 1260 the addresstranslator 1270 translates the address to device memory 1295. It is thenrouted to the device coherency engine 1280 of the device memorycontroller 1225.

2. The device coherency engine 1280 looks up the hardware coherencytracker 1285 to determine current ownership for the cache line(s).

3. If the lookup hits an entry in the OBP state, then the devicecoherency engine 1280 invokes the OBP-to-OBA state change flow describedbelow to change ownership to the accelerator device 1250. The devicecoherency engine 1280 then services the request from device memory 1295.

4. If the lookup hits an entry in an OBA state, then the devicecoherency engine 1280 immediately services the request from the devicememory 1295 (i.e., there is no need to snoop).

In one embodiment, the transfer of ownership from the accelerator 1250to the processor 1200 is triggered by hardware. If the accelerator 1250implements coherent caches 1260, then a snoop invalidate is performed.If the accelerator 1250 does NOT implement coherent caches (e.g., likemost GPGPUs), then no snooping is necessary. The device coherency engine1280 then allocates an entry in the hybrid coherency tracker 1285, in animplementation specific manner. An entry for the request is allocatedand its state is updated to OBP. If no entries are available, then anentry is selected for eviction and the OBP-to-OBA state change flow isinvoked for the eviction candidate. For a hybrid coherency tracker 1285with full coverage, the entry is updated to the OBP state.

In one implementation, the transfer of ownership from the processor 1200to the accelerator 1250 is triggered by hardware. First, a snoopinvalidate is performed in the processor caches 1215 (e.g., via acacheline flush operation). Upon receiving the snoop response, thehybrid coherency tracker 1285 is updated to OBA.

A hybrid coherency tracker 1285 of one implementation operates asfollows. For simplicity of description, it will be assumed that thecoherency tracker 1285 performs two state coherency tracking using theOBP and OBA states described above. Further, in one embodiment, thehybrid coherency tracker 1285 has full coverage for device memory 1295and uses an SRAM for efficient lookups. Because it has full coveragewhich fits in the SRAM, there is no need to handle evictions.

In one implementation, the hybrid coherency tracker 1285 is organized asrange-based tracker. For example, it may track a range of sequentialphysical addresses (e.g., like a page table entry). Alternatively, or inaddition, it may track a hashed range of addresses. Since there are noevictions, a reverse hash lookup is not necessary.

In one embodiment, in response to a request from processor 1200 todevice memory 1295, if the request misses the processor 1200 caches1215, the address is decoded by address translator 1220 to device memory1295 and is routed over the coherent interconnect 1240 to theaccelerator 1250. One implementation skips a lookup in the hybridcoherency tracker 1285 for processor 1200 requests to device memory1295, and assumes the cache line (or other data block) to be in the OBAstate. The device coherency engine 1280 invokes the OBA-to-OBP statechange flow (described below). It accesses the memory (for a readoperation) and returns a response back the processor 1200.

In one implementation, for a request from the accelerator device 1250 tothe device memory 1295, if the request misses the accelerator caches1260 and gets translated by the address translator 1270 to device memory1295, it is routed to the device coherency engine 1280 which performs alookup in the hybrid coherency tracker 1285. If the lookup hits an entryin the OBP state, then the device coherency engine 1280 uses theindirect access mode (IAM) described below to service the request. Ifthe lookup hits an entry in the OBA state, then the device coherencyengine 1280 services the request from device memory 1295 as usual. Thismode of operation realizes full device memory bandwidth.

As mentioned, one embodiment includes an indirect access mode where anaccelerator device 1250 can “indirectly” access the line in OBP statewithout changing the hybrid coherency tracker 1285 state. Each accessfrom accelerator device 1250 will generate a snoop request to theprocessor 1200. If processor 1200 has a modified line, it will write thedata back to the accelerator device 1250 but may retain a shared orexclusive copy of the line. If the processor 1200 has a clean line ordoesn't have the line then it will return a completion response withoutdata, and the device coherency engine 1280 can service the acceleratordevice 1250 request from the device memory 1295. This mode ofoperation—where each accelerator request to device memory is redirectedto the processor 1200 first, followed by a local device memory accesswill be referred to as the indirect access mode (IAM). When operating inIAM, accelerator bandwidth to the local device memory 1295 will belimited by the snoop rate of the coherent link 1240 between theprocessor 1200 and accelerator device 1250.

For a compute express link (CXL) interconnect 1240 with an acceleratordevice 1250 operating in indirect access mode, the accelerator device1250 routes requests targeted to accelerator memory 1295 towards theprocessor 1200. In one embodiment, these requests are formatted asread/write requests directed to host memory 1230. Link implementationsfor some embodiments may require that accelerator device 1250 generatesa snoop request to the processor 1200.

State change flow operates as follows for these embodiments. ForOBA-to-OBP, the transfer of ownership from the accelerator device 1250to processor 1200 is triggered by hardware. If the accelerator device1250 implements coherent caches 1260, then a snoop invalidate orcomparable operation invalidates the cache line in the caches 1260. Ifthe accelerator does NOT implement coherent caches (e.g., as with mostGPGPUs), then no snooping is necessary. The device coherency engine 1280then sets the corresponding entry in the hybrid coherency tracker 1285.This may be a write “1” operation; no atomic update or coherency trackerlookup is required.

While specific coherency operations such as snoop invalidate aredescribed herein, the underlying principles of the invention may usevarious other coherency operations. For example, a snoop read operationmay be used instead of snoop invalidate. A snoop read indicates therequestor's intent to retrieve a shared copy of the data, in contrast tosnoop invalidate which indicates that the requestor's intent is toattain exclusive ownership.

In contrast, OBP-to-OBA state changes are software managed in oneembodiment. Software sets a “Force IAM bit” in the accelerator device1250 that forces all accelerator requests to use indirect access mode(i.e., will ignore hybrid coherency tracker lookup). Software then setsthe “stop tracking bit”, to stop the processor 1200 requests fromsetting the hybrid coherency tracker to the OBP state and resets ALLhybrid coherency tracker entries to the OBA state. It then clears the“stop tracking bit” to start tracking processor 1200 accesses in thehybrid coherency tracker 1285 and may then flush out all memory deviceaddresses from all processor caches 1215 in accordance with theprocessor 1200 architecture (e.g., using WBINVD or CLFLUSH on x86processors). Rather than flushing all memory device addresses, oneembodiment selectively flushes only certain entries in the hybridcoherency tracker (e.g., specific device address ranges from processorcaches, potentially identified via an Address Space ID). In oneembodiment, software clears the “force IAM bit” in the acceleratordevice 1250 to resume normal flow

Embodiments of the invention include at least two ways to trigger theOBP-to-OBA state change flow. A timer may be maintained in oneembodiment to implement periodic triggers. For example, when the timerexpires, the software invokes the OBP-to-OBA state transition flow toreset the hybrid coherency tracker 1285 to the OBA state. The value ofthis timer may be programmable.

In addition, the accelerator device 1250 hardware may implement acounter or some predictor that monitors how often accelerator devicerequests to device memory 1295 have to use indirect access mode, becauseit hits an OBP state in HCT. It may also look at what percentage ofhybrid coherency tracker 1285 entries are in the OBP state and notifysoftware based on pre-defined thresholds. A specified management policyimplemented in software may trigger the OBP-to-OBA flow to reset thehybrid coherency tracker 1285 to the OBA state.

FIG. 12B illustrates an embodiment in which the processor 1200 comprisesa processor coherency engine 1281 with a hybrid coherency tracker 1286.In this embodiment, the processor coherency engine 1281 and hybridcoherency tracker 1286 may operate in substantially the same manner asthe device coherency engine 1280 and device hybrid coherency tracker1285, respectively In this embodiment, the coherency engines 1280-1281may communicate with one another to implement a distributed coherencyprotocol.

Thus, while the transactions described below are based on theimplementation in FIG. 12A, the same sets of transactions may beimplemented with respect to FIG. 12B, with the roles of the processor1200 and accelerator device 1250 reversed.

FIG. 13 illustrates an example sequence of transactions in which arequest generated by an accelerator device processing element 1255(e.g., GPU core, ALU, etc.) hits the hybrid coherency tracker 1285 inthe owned by processor (OBP) state to generate an indirect request. Inparticular, a read request is received by the device coherency engine1280 which performs a lookup in the hybrid coherency tracker 1285 anddetermines the OBP state. It then generates a processor snooptransaction. If the processor 1200 has a modified line, it will writethe data back to the accelerator in its response (but may retain ashared or exclusive copy of the line). If the processor has a clean lineor doesn't have the line then it will return a completion responsewithout data. In either case, the device coherency engine 1280 servicesthe accelerator device processing element 1255 request from the devicememory 1295 as illustrated.

FIG. 14 illustrates an example sequence of transactions in which theaccelerator processing element 1255 hits the hybrid coherency tracker1285 in the owned-by accelerator (OBA) state. Here, the device coherencyengine 1280 performs a lookup in the hybrid coherency tracker 1285 inresponse to a read request and receives an OBA state indication. Inresponse, it reads the data from device memory 1295 and provides thedata to the requesting accelerator processing element 1255.

FIG. 15 illustrates an example sequence of transactions in which thedevice coherency engine 1280 operates in indirect access mode (IAM),bypassing the hybrid coherency tracker 1285 and sending a readtransaction to the processor 1200. As mentioned, software may set a“Force IAM bit” in the accelerator device 1250 that forces allaccelerator requests to bypass the hybrid coherency tracker lookup andalso sets the “stop tracking bit”, to stop the processor 1200 requestsfrom setting the hybrid coherency tracker 1285 to the OBP state. In theillustrated transaction, there is a cache miss on the processor 1200which notifies the device coherency engine 1280. The device coherencyengine 1280 then reads the cache line from device memory 1295 andprovides it to the requesting processing element 1255.

In the foregoing specification, the embodiments of invention have beendescribed with reference to specific exemplary embodiments thereof. Itwill, however, be evident that various modifications and changes may bemade thereto without departing from the broader spirit and scope of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly, to be regarded in an illustrative rather thana restrictive sense.

EXAMPLES

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Example 1. A processing device comprising: one or more processingelements to process data; a memory controller to couple the one or moreprocessing elements to a device memory; an interconnect to couple theone or more processing elements to a host processor memory and to couplea host processor to the device memory; one or more device caches tostore cache lines read from the host processor memory and/or the devicememory; coherency circuitry to manage a state indication for each cacheline, the state indication to be set to a first value to indicateownership by the host processor and to be set to a second value toindicate ownership by the processing device, wherein the coherencycircuitry is to transfer ownership of a first cache line from theprocessing device to the host processor by updating the state indicationfrom the second value to the first value, the coherency circuitry toprovide indirect access to the cache line by the processing device whilethe state indication is set to the first value, the coherency circuitryto maintain the state indication at the first value until receiving arequest to change the state indication.

Example 2. The processing device of example 1 wherein the request tochange the ownership indication comprises a request generated bysynchronization software executed on the host processor or theprocessing device and/or synchronization circuitry configured on thehost processor and/or the processing device.

Example 3. The processing device of example 1 wherein to provideindirect access, the coherency circuitry is to snoop a cache subsystemof the host processor to determine a current state of the first cacheline.

Example 4. The processing device of example 3 wherein if the first cacheline is in a modified state, then one or more of the processing elementsare to receive the first cache line from the processor memory.

Example 5. The processing device of example 3 wherein if the first cacheline is in an unmodified state or if the host processor is not cachingthe first cache line, then one or more of the processing elements are toreceive the first cache line from the device memory.

Example 6. The processing device of example 1 wherein if the one or moredevice caches are implemented as coherent caches by the processingdevice, then the coherency circuitry is to perform a snoop invalidateoperation to invalidate the first cache line in the one or more devicecaches in response to the transfer of ownership of the first cache linefrom the processing device to the host processor.

Example 7. The processing device of example 1 wherein if the one or moredevice caches are not implemented as coherent caches by the processingdevice, then the coherency circuitry is to only update the ownershipindication from the second value to the first value.

Example 8. The processing device of example 1 wherein the processingelements comprise one or more of: graphics processing unit (GPU)execution units, tensor or matrix cores, digital signal processor (DSP)cores, network communication cores, and/or ray tracing cores.

Example 9. The processing device of example 1 wherein the coherencycircuitry is to transfer ownership of a first cache line from the hostprocessor to the processing device by updating the state indication fromthe first value to the second value, the coherency circuitry to maintainthe state indication at the first value until receiving a request tochange the state indication.

Example 10. A method comprising: setting a first state indicationassociated with a first cache in a first cache of a processing device toa second state indication to indicate ownership by the processingdevice, the processing device comprising a set of processing elements;transferring ownership of the first cache line from the processingdevice to a host processor by updating the state indication from thesecond state indication to a first state indication; providing indirectaccess to the cache line by the processing device while the stateindication is set to the first state indication, the coherency circuitryto maintain the first state indication until receiving a request tochange the first state indication.

Example 11. The method of example 10 wherein the request to change theownership indication comprises a software request generated bysynchronization software executed on the host processor or theprocessing device and/or synchronization circuitry configured on thehost processor and/or the processing device.

Example 12. The method of example 10 wherein providing indirect accesscomprises snooping a cache subsystem of the host processor to determinea current state of the first cache line.

Example 13. The method of example 12 wherein if the first cache line isin a modified state, then one or more of the processing elements are toreceive the first cache line from the processor memory.

Example 14. The method of example 12 wherein if the first cache line isin an unmodified state or if the host processor is not caching the firstcache line, then one or more of the processing elements are to receivethe first cache line from the device memory.

Example 15. The method of example 10 wherein if the one or more devicecaches are implemented as coherent caches by the processing device, thenperforming a snoop invalidate operation to invalidate the first cacheline in the one or more device caches in response to the transfer ofownership of the first cache line from the processing device to the hostprocessor.

Example 16. The method of example 10 wherein if the one or more devicecaches are not implemented as coherent caches by the processing device,then only updating the ownership indication from the second value to thefirst value.

Example 17. The method of example 10 wherein the processing elementscomprise one or more of: graphics processing unit (GPU) execution units,tensor or matrix cores, digital signal processor (DSP) cores, networkcommunication cores, and/or ray tracing cores.

Example 18. The method of example 10 wherein the coherency circuitry isto transfer ownership of a first cache line from the host processor tothe processing device by updating the state indication from the firstvalue to the second value, the coherency circuitry to maintain the stateindication at the first value until receiving a request to change thestate indication.

Example 19. A machine-readable medium having program code stored thereonwhich, when executed by a machine, causes the machine to perform theoperations of: setting a first state indication associated with a firstcache in a first cache of a processing device to a second stateindication to indicate ownership by the processing device, theprocessing device comprising a set of processing elements; transferringownership of the first cache line from the processing device to a hostprocessor by updating the state indication from the second stateindication to a first state indication; providing indirect access to thecache line by the processing device while the state indication is set tothe first state indication, the coherency circuitry to maintain thefirst state indication until receiving a request to change the firststate indication.

Example 20. The machine-readable medium of example 19 wherein therequest to change the ownership indication comprises a software requestgenerated by synchronization software executed on the host processor orthe processing device and/or synchronization circuitry configured on thehost processor and/or the processing device.

Example 21. The machine-readable medium of example 19 wherein providingindirect access comprises snooping a cache subsystem of the hostprocessor to determine a current state of the first cache line.

Example 22. The machine-readable medium of example 21 wherein if thefirst cache line is in a modified state, then one or more of theprocessing elements are to receive the first cache line from theprocessor memory.

Example 23. The machine-readable medium of example 21 wherein if thefirst cache line is in an unmodified state or if the host processor isnot caching the first cache line, then one or more of the processingelements are to receive the first cache line from the device memory.

Example 24. The machine-readable medium of example 19 wherein if the oneor more device caches are implemented as coherent caches by theprocessing device, then performing a snoop invalidate operation toinvalidate the first cache line in the one or more device caches inresponse to the transfer of ownership of the first cache line from theprocessing device to the host processor.

Example 25. The machine-readable medium of example 19 wherein if the oneor more device caches are not implemented as coherent caches by theprocessing device, then only updating the ownership indication from thesecond value to the first value.

Example 26. The machine-readable medium of example 19 wherein theprocessing elements comprise graphics processing unit (GPU) executionunits.

Example 27. The machine-readable medium of example 19 wherein theprocessing elements comprise one or more of: tensor or matrix cores,digital signal processor (DSP) cores, network communication cores,and/or ray tracing cores.

Example 28. The machine-readable medium of example 19 wherein thecoherency circuitry is to transfer ownership of a first cache line fromthe host processor to the processing device by updating the stateindication from the first value to the second value, the coherencycircuitry to maintain the state indication at the first value untilreceiving a request to change the state indication.

Embodiments of the invention may include various steps, which have beendescribed above. The steps may be embodied in machine-executableinstructions which may be used to cause a general-purpose orspecial-purpose processor to perform the steps. Alternatively, thesesteps may be performed by specific hardware components that containhardwired logic for performing the steps, or by any combination ofprogrammed computer components and custom hardware components.

As described herein, instructions may refer to specific configurationsof hardware such as application specific integrated circuits (ASICs)configured to perform certain operations or having a predeterminedfunctionality or software instructions stored in memory embodied in anon-transitory computer readable medium. Thus, the techniques shown inthe Figures can be implemented using code and data stored and executedon one or more electronic devices (e.g., an end station, a networkelement, etc.). Such electronic devices store and communicate(internally and/or with other electronic devices over a network) codeand data using computer machine-readable media, such as non-transitorycomputer machine-readable storage media (e.g., magnetic disks; opticaldisks; random access memory; read only memory; flash memory devices;phase-change memory) and transitory computer machine-readablecommunication media (e.g., electrical, optical, acoustical or other formof propagated signals—such as carrier waves, infrared signals, digitalsignals, etc.). In addition, such electronic devices typically include aset of one or more processors coupled to one or more other components,such as one or more storage devices (non-transitory machine-readablestorage media), user input/output devices (e.g., a keyboard, atouchscreen, and/or a display), and network connections. The coupling ofthe set of processors and other components is typically through one ormore busses and bridges (also termed as bus controllers). The storagedevice and signals carrying the network traffic respectively representone or more machine-readable storage media and machine-readablecommunication media. Thus, the storage device of a given electronicdevice typically stores code and/or data for execution on the set of oneor more processors of that electronic device. Of course, one or moreparts of an embodiment of the invention may be implemented usingdifferent combinations of software, firmware, and/or hardware.Throughout this detailed description, for the purposes of explanation,numerous specific details were set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the invention may be practiced without someof these specific details. In certain instances, well known structuresand functions were not described in elaborate detail in order to avoidobscuring the subject matter of the present invention. Accordingly, thescope and spirit of the invention should be judged in terms of theclaims which follow.

What is claimed is:
 1. A processing device comprising: one or moreprocessing elements to process data; a memory controller to couple theone or more processing elements to a device memory; an interconnect tocouple the one or more processing elements to a host processor memoryand to couple a host processor to the device memory; one or more devicecaches to store cache lines read from the host processor memory and/orthe device memory; coherency circuitry to manage a state indication foreach cache line, the state indication to be set to a first value toindicate ownership by the host processor and to be set to a second valueto indicate ownership by the processing device, wherein the coherencycircuitry is to transfer ownership of a first cache line from theprocessing device to the host processor by updating the state indicationfrom the second value to the first value, the coherency circuitry toprovide indirect access to the cache line by the processing device whilethe state indication is set to the first value, the coherency circuitryto maintain the state indication at the first value until receiving arequest to change the state indication.
 2. The processing device ofclaim 1 wherein the request to change the ownership indication comprisesa request generated by synchronization software executed on the hostprocessor or the processing device and/or synchronization circuitryconfigured on the host processor and/or the processing device.
 3. Theprocessing device of claim 1 wherein to provide indirect access, thecoherency circuitry is to snoop a cache subsystem of the host processorto determine a current state of the first cache line.
 4. The processingdevice of claim 3 wherein if the first cache line is in a modifiedstate, then one or more of the processing elements are to receive thefirst cache line from the processor memory.
 5. The processing device ofclaim 3 wherein if the first cache line is in an unmodified state or ifthe host processor is not caching the first cache line, then one or moreof the processing elements are to receive the first cache line from thedevice memory.
 6. The processing device of claim 1 wherein if the one ormore device caches are implemented as coherent caches by the processingdevice, then the coherency circuitry is to perform a snoop invalidateoperation to invalidate the first cache line in the one or more devicecaches in response to the transfer of ownership of the first cache linefrom the processing device to the host processor.
 7. The processingdevice of claim 1 wherein if the one or more device caches are notimplemented as coherent caches by the processing device, then thecoherency circuitry is to only update the ownership indication from thesecond value to the first value.
 8. The processing device of claim 1wherein the processing elements comprise one or more of: graphicsprocessing unit (GPU) execution units, tensor or matrix cores, digitalsignal processor (DSP) cores, network communication cores, and/or raytracing cores.
 9. The processing device of claim 1 wherein the coherencycircuitry is to transfer ownership of a first cache line from the hostprocessor to the processing device by updating the state indication fromthe first value to the second value, the coherency circuitry to maintainthe state indication at the first value until receiving a request tochange the state indication.
 10. A method comprising: setting a firststate indication associated with a first cache in a first cache of aprocessing device to a second state indication to indicate ownership bythe processing device, the processing device comprising a set ofprocessing elements; transferring ownership of the first cache line fromthe processing device to a host processor by updating the stateindication from the second state indication to a first state indication;providing indirect access to the cache line by the processing devicewhile the state indication is set to the first state indication, thecoherency circuitry to maintain the first state indication untilreceiving a request to change the first state indication.
 11. The methodof claim 10 wherein the request to change the ownership indicationcomprises a software request generated by synchronization softwareexecuted on the host processor or the processing device and/orsynchronization circuitry configured on the host processor and/or theprocessing device.
 12. The method of claim 10 wherein providing indirectaccess comprises snooping a cache subsystem of the host processor todetermine a current state of the first cache line.
 13. The method ofclaim 12 wherein if the first cache line is in a modified state, thenone or more of the processing elements are to receive the first cacheline from the processor memory.
 14. The method of claim 12 wherein ifthe first cache line is in an unmodified state or if the host processoris not caching the first cache line, then one or more of the processingelements are to receive the first cache line from the device memory. 15.The method of claim 10 wherein if the one or more device caches areimplemented as coherent caches by the processing device, then performinga snoop invalidate operation to invalidate the first cache line in theone or more device caches in response to the transfer of ownership ofthe first cache line from the processing device to the host processor.16. The method of claim 10 wherein if the one or more device caches arenot implemented as coherent caches by the processing device, then onlyupdating the ownership indication from the second value to the firstvalue.
 17. The method of claim 10 wherein the processing elementscomprise one or more of: graphics processing unit (GPU) execution units,tensor or matrix cores, digital signal processor (DSP) cores, networkcommunication cores, and/or ray tracing cores.
 18. The method of claim10 wherein the coherency circuitry is to transfer ownership of a firstcache line from the host processor to the processing device by updatingthe state indication from the first value to the second value, thecoherency circuitry to maintain the state indication at the first valueuntil receiving a request to change the state indication.
 19. Amachine-readable medium having program code stored thereon which, whenexecuted by a machine, causes the machine to perform the operations of:setting a first state indication associated with a first cache in afirst cache of a processing device to a second state indication toindicate ownership by the processing device, the processing devicecomprising a set of processing elements; transferring ownership of thefirst cache line from the processing device to a host processor byupdating the state indication from the second state indication to afirst state indication; providing indirect access to the cache line bythe processing device while the state indication is set to the firststate indication, the coherency circuitry to maintain the first stateindication until receiving a request to change the first stateindication.
 20. The machine-readable medium of claim 19 wherein therequest to change the ownership indication comprises a software requestgenerated by synchronization software executed on the host processor orthe processing device and/or synchronization circuitry configured on thehost processor and/or the processing device.
 21. The machine-readablemedium of claim 19 wherein providing indirect access comprises snoopinga cache subsystem of the host processor to determine a current state ofthe first cache line.
 22. The machine-readable medium of claim 21wherein if the first cache line is in a modified state, then one or moreof the processing elements are to receive the first cache line from theprocessor memory.
 23. The machine-readable medium of claim 21 wherein ifthe first cache line is in an unmodified state or if the host processoris not caching the first cache line, then one or more of the processingelements are to receive the first cache line from the device memory. 24.The machine-readable medium of claim 19 wherein if the one or moredevice caches are implemented as coherent caches by the processingdevice, then performing a snoop invalidate operation to invalidate thefirst cache line in the one or more device caches in response to thetransfer of ownership of the first cache line from the processing deviceto the host processor.
 25. The machine-readable medium of claim 19wherein if the one or more device caches are not implemented as coherentcaches by the processing device, then only updating the ownershipindication from the second value to the first value.
 26. Themachine-readable medium of claim 19 wherein the processing elementscomprise graphics processing unit (GPU) execution units.
 27. Themachine-readable medium of claim 19 wherein the processing elementscomprise one or more of: tensor or matrix cores, digital signalprocessor (DSP) cores, network communication cores, and/or ray tracingcores.
 28. The machine-readable medium of claim 19 wherein the coherencycircuitry is to transfer ownership of a first cache line from the hostprocessor to the processing device by updating the state indication fromthe first value to the second value, the coherency circuitry to maintainthe state indication at the first value until receiving a request tochange the state indication.